1. Field of the Invention
The present invention relates to a comparator, an AD conversion circuit, a semiconductor device, and an image capturing apparatus. In particular, the invention relates to the technology of a hysteresis circuit to be formed in a comparator and an AD conversion circuit.
2. Description of the Related Art
Conventionally, some comparators for use in multi-bit AD conversion circuits have incorporated a hysteresis circuit for reducing noise effect for the sake of improved operation stability (for example, see Japanese Patent Laid-Open Publication No. Hei 5-167400). The reason is that in multi-bit AD conversion circuits beyond 10 bits in particular, the increasing number of bits makes bit-by-bit voltage steps smaller and thus increases the possibility of noise-induced malfunctions. The conventional hysteresis circuit switches its reference voltage to a voltage value higher than a threshold when its input voltage increases and switches the reference voltage to a voltage value lower than the threshold when the input voltage decreases. Thus, even if the input voltage fluctuates in value near the threshold, the output will not alternate between high level and low level. As a result, stable output is obtained.
Nevertheless, there has been the disadvantage that the conventional multi-bit AD conversion circuits have a plurality of switches, such as transistors, for realizing the hysteresis circuit, with an increase in circuit scale accordingly. There has also been the possibility that the increased number of switches can complicate the design and control.